Summary
This project provides a highly configurable, portable, open-source (VHDL) sliding-window generator. The VHDL entity includes configuration options for image sizes, window sizes, data width, number of parallel windows, among others (see documentation). The image and window sizes can also be changed dynamically. Given an input image, the window generator will create a set of output windows that correspond to "sliding" the window across the image. This type of operation is common in many signal-processing applications (e.g., convolution). One of the main contributions of this project is support for any number of parallel windows.
This project provides the VHDL source code associated with the paper:
Greg Stitt, Eric Schwartz, Patrick Cooke. A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs, ACM Transactions on Reconfigurable Technology and Systems (TRETS): Special Issue on Reconfigurable Components with Source Code, To Appear
If you use this code in a project, we would appreciate a reference to this paper.
Abstract
Sliding-window applications, an important class of the digital-signal processing domain, are highly amenable to pipeline parallelism on field-programmable gate arrays (FPGAs). Although memory bandwidth often restricts parallelism for many applications, sliding-window applications can leverage custom buffers, referred to as sliding-window generators, that provide massive input bandwidth that far exceeds the capa- bilities of external memory. Previous work has introduced a variety of sliding-window generators, but those approaches typically generate at most one window per cycle, which significantly restricts parallelism. In this paper, we address this limitation with a parallel sliding-window generator that can generate a configurable number of windows every cycle. Although in practice the number of parallel windows is limited by memory bandwidth, we show that even with common bandwidth limitations, the presented generator enables near- linear speedups up to 16x faster than previous FPGA studies that generate a single window per cycle, which were already in some cases faster than graphics-processing units (GPUs) and microprocessors.
Instructions
Please read the corresponding paper for usage instructions. The included README file also includes an explanation of the interface and configuration options.
Planned Extenstions
- Support for VHDL 2008. The entity requires 2D unconstrained arrays (images) of an unconstrained type (pixel widths), which are supported in earlier versions of VHDL. As a workaround, the current version converts these arrays into large 1D vectors, which require specialized code for indexing.
- Optimizations for specialized configuration options. For example, when generating a single window at a time, it is likely that some of the circuit can be eliminated. Similarly, when only using one image and/or window size, the functionality for dealing with different runtime sizes can be eliminated.
Feel free to suggest extensions, or to commit them to the repository on your own. We hope for this entity to be widely used for FPGA-based signal-processing applications.
License
This project is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
window_gen is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.